Digital data signals, when transmitted, frequently contain jitter, that is, a distortion of the signal caused by poor synchronization. If jitter or other noise is significant the digital data signals more closely resemble analog signals. The process of locking onto or acquiring the clock from a data signal, and thus, compensating for the jitter, is referred to as recovering the clock signal in the data signal. A Clock Recovery (CR) circuit for recovering the clock signal with improved jitter tolerance often employs a Voltage Controlled Oscillator (VCO), which has a large modulation bandwidth, to lock onto the digital data signal. The use of the VCO is normally considered advantageous, as the VCO has a large frequency tolerance, which compensates for the jitter in the data signal. The large frequency tolerance of the VCO, however, is also a drawback, because it increases the frequency acquisition time when used with a digital data signal having a low Signal to Noise Ratio (SNR). In some instances, the wide frequency tolerance of the VCO can prevent the clock recovery circuit from locking onto the digital data signal.
One solution to the problem of using a VCO to lock onto a digital data signal with a low SNR has been to combine the VCO with a Voltage Controlled Crystal Oscillator (VCXO), which is more stable, in a combination circuit. In the combination circuit, the VCXO acquires the clock from the data signal, in what is known as the “fast acquisition” state, while the VCO locks onto the data signal once the VCXO has acquired the clock from the data signal, in what is known as the “locked” or “steady” state. The combination circuit can thus be said to operate in two modes: the normal mode and the fast acquisition mode. The combination circuit limits the frequency error of the VCO since the VCXO, which has a small modulation bandwidth, defines the frequency acquisition time of the digital circuit, and not the VCO. The combination circuit improves the lock-in behavior of a digital data signal with a low SNR as compared to a circuit with only a VCO.
A combination circuit encounters significant difficulties, however, when the input data, which has been valid for a predetermined length of time, suddenly becomes invalid. When this occurs, the circuit is said to enter into a “holdover” state. In the holdover state, the VCO and the VCXO are locked to the data frequency, and are no longer responsive to the digital data signal. The VCO follows the VCXO, which is free running. When valid data later appears in the digital data signal, the VCO and the VCXO must enter the fast acquisition state in order to reacquire the clock from the data signal. The reacquisition of the clock can take a long time. The relatively small modulation bandwidth of the VCXO is the chief factor causing the long reacquisition time.
The aforementioned problem is acute for clock recovery circuits that are used with data signals having very low SNR values. It is particularly problematic when the circuits are used in optical networking applications such as Synchronous Optical Network (SONET) and Synchronous Digital Hierarchy (SDH) systems, which use forward error correction (FEC). The clock recovery circuit in such applications must reliably lock onto signals with very low SNR values with a relatively short frequency acquisition time.